1. Field of Invention
The present invention relates to a display panel control circuit, in particular a display panel control circuit which separates the current sourcing path and the current sinking path by two different resistor circuits and providing two diodes respectively in the two paths.
2. Description of Related Art
A basic driving voltage waveform for driving pixels in a LCD display is as shown by the waveform 1 in FIG. 1, wherein the driving voltage switches between a high level and a low level. For a better performance in driving pixels, a “gate shaping” technique is proposed. When the driving voltage switches from low level to high level, the gate shaping technique pre-raises the driving voltage to a mid level, and when the driving voltage switches from high level to low level, the gate shaping technique pre-drops the driving voltage to a mid level, so as to reduce the gap between level switching. If the driving voltage switches its levels too fast (switches between levels with a large gap in a short time), the feed through effect caused by parasitic capacitance may affect the pixel grayscale and cause it to deviate. In FIG. 1, the vertical scale represents voltage and the horizontal scale represents time. The waveform 1 is a waveform without gate shaping, and the waveforms 2-4 are waveforms with various gate shaping types (such as the rising gate shaping A and the falling gate shaping B) which are designed according to different practical needs.
Referring to FIG. 2, a prior art display panel control circuit 10 is shown. The waveforms shown in FIG. 1 are to be generated at an output terminal VG. The voltages VGH and VGL are high voltage source and low voltage source respectively, which correspond to the high level and the low level shown in FIG. 1. Assuming that the circuit 10 is to generate the waveform 2 of FIG. 1, it operates as follows: First, the switch ML is turned on and the switches MH, MD1, and MD2 are turned off to generate the low level of the waveform 2. Next, the switches MH and ML are turned off and the switches MD1 and MD2 are turned on, so that a voltage terminal AVDD charges the output terminal VG to generate the rising gate shaping A in the waveform 2, wherein the slope of the rising gate shaping A is determined by the resistor R: the output driving voltage rises faster when the resistor R has a smaller resistance, and the output driving voltage rises slower when the resistor R has a higher resistance. Next, the switch MH is turned on and the switches M1, MD1 and MD2 are turned off, so that the high voltage source VGH supplies power to the output terminal VG to generate the high level of the waveform 2. Next, before switching the voltage at the output terminal VG to low level, the switches MH and ML are turned off and the switches MD1 and MD2 are turned on so that the output terminal VG discharges toward the voltage terminal AVDD to generate the falling gate shaping B in the waveform 2, and the slope of the falling gate shaping B is likewise determined by the resistor R. The aforementioned prior art has a drawback that the rising gate shaping A and the falling gate shaping B are both controlled by the same resistor R, so the rising and falling slopes can not be set differently.
Referring to FIG. 3, another prior art display panel control circuit 20 is shown. Compared to the display panel control circuit 10, the display panel control circuit 20 is different in that: the resistor R is replaced by a parallel circuit including a voltage rising resistor Rr which is connected is series with a voltage rising diode Dr, and a voltage falling resistor Rf. The rising slop of the rising gate shaping A is decided by the resistance of the parallel circuit; the falling slope of the falling gate shaping B is decided by the resistance of the voltage falling resistor Rf. Although in this circuit the rising and falling slopes can be set differently, the setting is complicated because it requires calculating the resistance of the parallel circuit and the rising slope and the falling slope affects each other.
Referring to FIG. 4, another prior art display panel control circuit 30 is shown. Compared to the display panel control circuit 10, the voltage falling resistor Rf and the switches MD1 and MD2 correspond to the resistor R and the switches MD1 and MD2 shown in FIG. 2, but the display panel control circuit 30 further includes another group of voltage rising resistor Rr and switches MR1 and MR2. The rising gate shaping is generated by conducting the voltage rising resistor Rr and the switches MR1 and MR2, and the falling gate shaping is generated by conducting the voltage falling resistor Rf and the switches MD1 and MD2. In short, the voltage rising resistor Rr and the voltage falling resistor Rf respectively decide the slopes of the rising gate shaping and the falling gate shaping, so they can be set differently without complicated calculation. Although this prior art has the advantage of easier setting, the additional switches MR1 and MR2, which require to be high voltage transistors, significantly increase the cost.
Hence, it is desired to provide a simple and low cost display panel control circuit wherein the slopes of the rising gate shaping and the falling gate shaping can be set differently and easily.